1. Field of the Invention
The present invention relates to a bus drive circuit for driving a bus for transmitting information of plural circuit blocks or elements constituting a semiconductor integrated circuit, a receiver circuit for receiving signals transmitted through the bus, and a bus system using such bus drive circuit and receiver circuit, and more particularly to a bus drive circuit composed by using MOS transistors for reducing the logical amplitude of the signals transmitted through the bus, a receiver circuit using MOS transistors, and a bus system using such bus drive circuit and receiver circuit.
2. Description of the Background Art
Recently as the degree of integration of semiconductor integrated circuit (hereinafter called IC) is advanced, the quantity of data of IC that can be processed at a time is increased. For smooth exchange of data between circuit blocks inside the IC, along with increase of quantity of data processed by the IC, the width of bus (number of data lines) for transmitting the information by linking the circuit blocks is also increased.
FIG. 16 is a block diagram showing the constitution of a conventional bus system. In FIG. 16, reference numeral 1 is a bus composed of n data lines, 2 to 5 are circuit blocks provided in an IC, 6, 7 are data line drive circuits for driving the data lines of the bus 1 depending on the output of the circuit block 2, 8, 9 are data buffers for taking in the information from the data lines of the bus 1, and 10, 11 are data line drive circuits for driving the data lines of the bus 1 depending on the output of the circuit block 4. The bus drive circuit contains at least one data line drive circuit.
For example, the data line drive circuits 6, 7 and data line drive circuits 10, 11 are required so that their outputs be in high impedance state unless driving the bus 1 because their output lines are wired OR. To adjust the timing to set the data line drive circuits at high impedance, the data line drive circuits 6, 7 are controlled by signal E1, and the data line drive circuits 10, 11 are controlled by signal E2. The data line drive circuit for giving the output of a same circuit block to the bus is not required to be controlled always by a same signal, and it may be controlled by two signals E3, E4 as in, for example, a bus drive circuit 13. Or, as in the circuit block 5, a bus drive circuit 13 and a receiver circuit 12 may be both provided in one circuit block. Signals E1 to E4 for controlling the data line drive circuit are given from a control circuit not shown.
Generally, the wiring length of a bus is as long as several millimeters, and the parasitic capacity is large, and its charging and discharging current is not small. It is because the increase of charging and discharging current along with increase of bus width is becoming a serious problem that much is recently studied about the curtailment of current consumption of the bus.
A constitution of a bus system proposed in relation to curtailment of current consumption of the buses are shown in FIG. 17A and FIG. 17B. Specifically, FIG. 17A shows a circuit diagram of a bus drive circuit for transmitting two-bit information, and FIG. 17B shows a constitution of a bus drive circuit for transmitting information of four bits or more. The bus systems shown in FIG. 17A and FIG. 17B are disclosed, for example, by Hiroyuki Yamauchi, Hironori Akamatsu and Tsutomu Fujita, "A Low Power Complete Change-Recycling Bus Architecture for Ultra-High Data Rate ULSIs," 1994 Symposium on VLSI Circuits Digest of Technical Papers, pp. 21-22. In FIG. 17A, PM0 to PM4 are PMOS transistors, NM0 to NM4 are NMOS transistors, 20 to 23 are data lines, and Cp0, Cp1, Cn0, Cn1 are parasitic capacities of the data lines 20 to 23 composing each bus. Each data line of the buses shown in FIG. 17A and FIG. 17B is driven by either one of the two kinds of data line drive circuit. That is, one is a data line drive circuit PDR composed of P channel MOS transistors, and the other is a data line drive circuit NDR composed of N channel MOS transistors. In other words, the bus drive circuit is composed of plural sets of data line drive circuits PDR, NDR. When transmitting a signal through the bus, each data line drive circuit uses complementary signals in input and output. To the input of the data line drive circuit PDR, a signal Pin0 and its inverted signal Pin1 are given, and at the output, a signal Pout0 and its inverted signal Pout1 are generated. Similarly, to the input of the data line drive circuit NDR, a signal Nin0 and its inverted signal Nin1 are given, and at the output, a signal Nout0 and its inverted signal Nout1 are generated. EQP is an equalizing signal of the data line drive circuit PDR, and EQN is an equalizing signal of data line drive circuit NDR, and both are mutually complementary.
The operation of this circuit is described. For the simplicity of explanation, a bus of two-bit composition shown in FIG. 17A is mentioned. In this case the bus drive circuit of one circuit block is composed of one data line drive circuit PDR and one data line drive circuit NDR. A terminal PH of the data line drive circuit PDR is connected to a power source potential VDD, and a terminal NL of the data line drive circuit NDR is connected to a grounding potential GND. A terminal PL of the data line drive circuit PDR and a terminal NH of the data line drive circuit NDR are connected with each other.
In an initial state, the terminal PH is supposed to be at power source potential VDD, the terminal NL at grounding potential GND, and the terminals PL and NH at VDD/2. The parasitic capacities Cp0, Cp1, Cn0, Cn1 are supposed to be all equal in quantity. FIG. 18 shows a timing chart of the circuit shown in FIG. 17A. One cycle of operation of the data line drive circuits PDR, NDR is composed of an equalizing period Ep and a data transfer period Ev. First, in the equalizing period Eq, the equalizing signal EQN is at high level and the equalizing signal EQP is at low level, and the data lines 20, 21 are equalized, and also the data lines 22 23 are equalized. That is, in the data line drive circuit PDR, as the P channel MOS transistor PM4 conducts, the data lines 20, 21 are connected. The potential of the data lines 20, 21 is determined as follows by the rule of conservation of electric charges accumulated in the parasitic capacities Cp0 and Cp1. Between the parasitic capacity Cp0 and the electric charge Qp0 before being equalized, there is a relation of Qp0=Cp0.multidot.VDD. On the other hand, between the parasitic capacity Cp1 and the electric charge Qp1 before being equalized, there is a relation of Qp1=Cp1.multidot.VDD/2. The potential V of the data lines 20, 21 after being equalized is given in the form of V.multidot.(Cp0-Cp1)=Qp0-Qp1, that is, the potential V is 3.multidot.VDD/4. In the data line drive circuit NDR, as the N channel MOS transistor NM4 conducts, data lines 22, 23 are connected. The potential of the data lines 22 23 is VDD/4. At this time, in order that the other transistors than the transistors PM4, NM4 for equalizing may not conduct, both signals Pin0, Pin1 are at high level, while signals Nin0, Nin1 are both at low level.
In the next period of the equalizing period, that is, in the data transfer period Ev, the data is transferred. At this time, a potential depending on the data being transmitted is given to each input of the data line drive circuits PDR, NDR. For example, signal Pin0 is supposed to be at high level, and signal Pin1 at low level. Similarly, the signal Nin0 is supposed to be at high level, and signal Nin1 at low level. At this time, all of P channel MOS transistors PM1, PM2 and N channel MOS transistors NM0, NM3 conduct, and the parasitic capacity of the data line 21 is charged, and the output signal Pout1 becomes nearly equal to VDD, while the parasitic capacity of the data line 23 is discharged, and the output signal Nout1 becomes nearly equal to GND.
The data line 20 and data line 22 are connected through the transistors PM2, NM0. Seeing that the signal Pout0 outputted from the data line 20 at the equalizing point was 3.multidot.VDD/4, and the signal Nout0 outputted from the data line 22 was VDD/4, the potential of the mutually connected data lines 20, 22 is found to be VDD/2.
When the input signal Pin0 is at low level and its complementary signal or input signal Pin1 is at high level, the signal Pout0 outputted through the data line 20 is VDD, and the signal Pout1 outputted through the data line 21 is VDD/2. When the input signal Nin0 is at low level and the input signal Nin1 is at high level, the signal Nout0 outputted through the data line 22 is GND, and the signal Nout1 outputted through the data line 23 is VDD/2.
At the data receiver side, the potential difference of these complementary signals is detected. Thus, in the data transfer period, depending on the input signals Pin0, Pin1, mutually complementary output signals Pout0, Pout1 are outputted to a pair of data lines 20, 21, and depending on the input signals Nin0, Nin1, mutually complementary output signals Nout0, Nout1 are outputted to a pair of data lines 22, 23. If the bus width exceeds two bits, that is, if the bus has two pairs or more of data lines, it is extended by overlaying the data line drive circuits PDR, NDR shown in FIG. 17A in series. For example, by combining as shown in FIG. 17B when the bus width is n bits (n being an even number), n/2 data line drive circuits PDR are connected in series from the power source side, and n/2 data line drive circuits NDR are connected in series therefrom to the grounding side.
Seeing the operation of this bus system from other point of view, the electric charge is exchanged between data lines composing one pair of data lines in the equalizing period, and the electric charge is exchanged between the adjacent pair of data lines in the data transfer period. When the bus width is two bits as shown in FIG. 17A, the electric charge is supplied from the power source line for feeding the power source potential VDD in the data transfer period into the parasitic capacity Cp0 of the data line 20, and in the next equalizing period, the charge is transferred from the parasitic capacity Cp0 to the parasitic capacity Cp1 of the data line 21. Furthermore, the charge is transferred from the parasitic capacity Cp0 of the data line 20 to the parasitic capacity Cn0 of the data line 22 in the next data transfer period, and the charge is further transferred from the parasitic capacity Cn0 of the data line 22 into the parasitic capacity Cn1 of the data line 23 in the next equalizing period. Consequently, the charge is discharged into the grounding line for supplying the grounding potential GND from the parasitic capacity Cn1 of the data line 23 in the next data transfer period.
In this way, the electric charge consumed in one cycle is only the first charge charged into the parasitic capacity Cp0 from the power source line for feeding the power source potential VDD, in other words, only the charge discharged into the grounding line for feeding the grounding potential GND from the parasitic capacity Cn1. That is, it is only the electric charge necessary for pulling up the output signal Pout0 outputted through the data line 20 from 3.multidot.VDD/4 to VDD, and hence the current consumption is saved greatly as compared with the data line drive circuit composed of inverter shown in FIG. 16.
The conventional bus drive circuit is thus constituted, and hence involves the following problems. First, if using the conventional bus drive circuits shown in FIG. 17A and FIG. 17B, the output signals must be complementary, and two data lines are needed for transmitting one-bit data. Recently, the bus width tends to increase notably, and the area occupied by the bus in the IC cannot be ignored, and the increase in the number of data lines per bit is very disadvantageous for increasing the bus width. Using the conventional bus system shown in FIG. 16, such problem can be avoided, but the power consumption cannot be curtailed.
Secondly, if using the bus drive circuits shown in FIG. 17A and FIG. 17B, the potential of the data lines must be set at specific potential, and it takes time to initialize the data lines. As shown in the description of operation above, the bus drive circuits PDR, NDR do not operate as desired unless the potential of the terminal PH of the data line drive circuit PDR is VDD, the potential of the terminal NL of the data line drive circuit NDR is GND, and the potential of the terminals PL and NL is VDD/2 in the initial state. When turning on the power source, the potential of all data lines is unstable, and equalizing and transfer of dummy data must be repeated a considerable number of times in order to define the data line potentials at desired values.
A third problem relates to the operating speed of the bus drive circuit. To use the bus drive circuits shown in FIG. 17A and FIG. 17B, it is required to pass two MOS transistors connected in series when transferring the electric charge between adjacent pairs of data lines in the data transfer period. Or, along with the increase in the number of bits, when the data line drive circuits are stacked up in series, some of the multiple bus drive circuits being stacked up are remote from the power source. Because of the body effect of the MOS transistor, the driving force is lowered in the data line drive circuit PDR remote from the power source, and the driving force is lowered in the data line drive circuit NDR remote from the grounding potential. Hence, a longer time is needed until the data line potentials are established, and to cope this, ultimately, the operating speed of the bus system must be slowed down.
Relating to the third problem, it leads to a fourth problem concerning the operating speed of the receiver circuit. The potential difference between two data lines for composing the pair of data line is VDD/n where n is the bus width, and as the bus width increases, a receiver circuit of high performance capable of detecting a smaller potential difference is needed. Generally, as the potential difference becomes smaller, the time for detecting it becomes outstandingly long. Besides, as the potential difference becomes smaller, the effect of very small noise existing in the data line cannot be ignored, and hence for practical reason, the applicable bit width is limited accordingly.